This application claims the benefit of Korean Application No. 2000-56149 filed Sep. 25, 2000 in the Korean Patent Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to an apparatus for and a method of selective disturbance compensating a signal reproduced from an optical recording medium, and more particularly, to a selective disturbance compensating apparatus and a 3T-correcting method, in which tilt or asymmetry which occurs in the reproduced signal is compensated by selectively using an equalizer or T-correcting circuit.
2. Description of the Related Art
An example of a conventional disturbance compensating circuit for an optical recording medium is shown in FIG. 1. The disturbance compensating circuit includes an analog-to-digital converter (ADC) 100, a direct current (DC) offset canceller 110, an adder 120, an adaptive equalizer 130, a Viterbi decoder 140, and a phase-locked loop circuit (PLC) 150. The ADC 100 converts an analog signal read from the optical recording medium to digital data with a predetermined sampling cycle. The DC offset canceller 110 extracts a DC offset from the digital data output from the ADC 100. The adder 120 adds the digital data output from the ADC 100 with a negative DC offset signal output from the DC offset canceller 110 to output digital data from which the DC offset is removed. The adaptive equalizer 130, which is for compensating for an error existing in the DC offset-canceled digital data, compensates for tilt of the optical recording medium, like a general error correcting apparatus used in, for example, a hard disk drive (HDD). The Viterbi decoder 140 compensates for an asymmetry component of the signal output from the adaptive equalizer 130. The above-described structure is a typical partial response maximum likelihood (PRML) detection structure. A phase-locked signal generated by the phase-locked circuit 150 is used as a clock of this circuit.
Since the conventional disturbance compensating circuit adopts high-performance detectors such as the adaptive equalizer 130 and Viterbi decoder 140, its overall detection performance, particularly with respect to a tangential tilt, is excellent. However, there is a problem of degrading of the adaptive PRML detection performance of the adaptive equalizer 130 where serious asymmetry occurs. In addition, there is a problem in that the circuit becomes large.
To solve the above-described problems, it is an object of the present invention to provide a selective disturbance compensating apparatus for reproduction from an optical recording medium and a method of 3T-correcting, in which detection performance with respect to tilt and asymmetry is improved by selectively using an equalizer and a T-correcting circuit. Additional objects and advantages of the invention will be set forth in part in the description which follows, and, in part, will be obvious from the description, or may be learned by practice of the invention.
To achieve the above and other objects of the present invention, there is provided a selective disturbance compensating apparatus for use in reproduction from an optical recording medium for compensating for the disturbance of a signal read from the reproducing medium and converted into a digital signal. A direct current (DC) offset canceller extracts a DC offset from the signal and cancels the DC offset. A switching unit performs an appropriate switching operation according to whether distortion caused by asymmetry of the offset-canceled signal is above a predetermined reference level. A first signal processor is selected by the switching unit where the distortion caused by asymmetry of the offset-canceled signal is below the predetermined reference level to equalize the offset-cancelled signal. A second signal processor receives the offset-canceled signal to correct the asymmetry of the received signal where the distortion caused by asymmetry of the signal is above the predetermined reference level, and receives the signal output from the first signal processor where the first signal process is selected by the switching unit to correct the asymmetry of the signal from the first signal processor.
Preferably, the first signal processor compares a predetermined expected value with an actual detected value and compensates for a difference (error) between the compared signals so that the difference converges to zero.
Preferably, the first signal processor is an equalizer. In the equalizer, an adaptive filter filters the offset-canceled signal with a variable tap coefficient and outputs the filtered signal. A delay register delays the signal passed through the adaptive filter for a predetermined period of time and outputs the delayed signal. A level detector determines a level value based on a plurality of delayed signals stored in the delay register and outputs a determined level value. A selecting unit outputs one of the plurality of delayed signals as a detected value based on the determined level value. An expected value storing unit outputs a predetermined expected value based on the determined level value. A comparing unit compares the detected value and the expected value and outputs a difference signal based on the comparison. A coefficient calculator calculates tap coefficients for the adaptive filter by applying a predetermined adaptive algorithm to the difference signal output from the comparing unit and the offset-canceled signal.
The second signal processor is preferably a 3T-correcting unit. In the 3T-correcting unit, a first register determines a sign of the selected signal at every detection clock, stores the results of the determination, and shifts stored values by 1 bit at the next detection clock. As described above, the selected signal is one of the offset-canceled signal and the equalized signal as selected by the switching unit. A second register stores an absolute value of the selected signal at every detection clock and shifts stored values to next storing locations at the next detection clock. A T-detecting circuit detects whether the selected signal is a 1T or a 2T signal using the values stored in the first and second registers. A first substituting circuit corrects the selected signal into a 3T signal if the selected signal is determined to be a 1T signal, by inverting the sign of signals at adjacent detection time points (i.e. previous and subsequent in time) from the 1T signal. A second substituting circuit corrects the selected signal into a 3T signal if the selected signal is determined to be a 2T signal, by comparing the absolute value of signals at the adjacent detection time points from the 2T signal and inverting the sign of the adjacent signal having a smaller absolute value than the absolute value of the other adjacent signal.
Preferably, in the 3T-correcting unit, a first register determines the sign of the offset-canceled signal at every detection clock, stores the result of the determination, and shifts stored values by 1 bit at the next detection clock. A second register stores the absolute value of the selected signal at every detection clock, and shifts the stored values to next storing locations at the next detection clock. A T-detecting circuit detects whether a portion of the selected signal is a 1T or a 2T signal using the values stored in the first and second registers. A first substituting circuit changes an amplitude of signals at adjacent detection time points from the portion of the selected signal to xe2x80x9c1xe2x80x9d and outputs the value of xe2x80x9c1xe2x80x9d if the portion of the selected signal is determined to be a 1T signal by the T-detecting circuit. A second substituting circuit compares an absolute value of signals at adjacent detection time points from the portion of the selected signal if the portion of the selected signal is determined to be a 2T signal by the T-detecting circuit, and changes the amplitude of the adjacent signal having the smaller absolute value than the other adjacent signal to 1, and outputs the value of xe2x80x9c1xe2x80x9d. An operator performs an exclusive-OR-operation (XOR) on the output value of the first or second substituting circuit and the sign of the input signal for 3T-correction, i.e., the selected signal.
To achieve the above and other objects of the present invention, there is provided another embodiment of a selective disturbance compensating apparatus for reproduction from an optical recording medium for compensating for the disturbance of a signal read from the reproducing medium and converted into a digital signal. A direct current (DC) offset canceller cancels a DC offset from the digital signal and a first signal processor equalizes the offset-canceled signal. A first switching unit selects one of the offset-canceled signal and the equalized signal according to a comparison of a level of distortion caused by asymmetry of the offset-canceled signal with a predetermined reference level. A second signal processor corrects the asymmetry of the selected signal and outputs a first corrected result. A Viterbi decoder corrects the asymmetry of the equalized signal and outputs a second corrected result. A second switching unit selects one of the first and second corrected results to output an asymmetry corrected signal.
the present invention is also achieved by a 3T-correcting method of compensating for distortion caused by asymmetry of an input signal in reproduction from an optical recording medium, the method comprising: determining a sign of a signal at every detection time point; if an input signal is determined to be a 1T signal by the determination of the sign, correcting the 1T signal into a 3T signal by inverting the sign of signals at the adjacent detection time points from the 1T signal; and if an input signal is determined to be a 2T signal by the determination of the sign, correcting the 2T signal into a 3T signal by comparing the absolute value of signals at the adjacent detection time points from the 2T signal and inverting the sign of the adjacent signal having a smaller absolute value than the absolute value of the other adjacent signal.